I/O Architect Engineer

As an I/O Architect Engineer, you will have the opportunity to work in a dynamic group that influences and guides technical teams across multiple functional groups. Specific duties include:
• Being responsible for architecture definition and refinement of I/O PHY cells from concept through production• Needing to provide technical coordination and issue resolution across multiple functional teams including Circuits, System Engineering, Signal Integrity, Verification, Logic, and Marketing• Being responsible for delivering specifications and work on next generation designs
REQUIREMENTS
An I/O Architect Engineer’s background should encompass:
• BS & 7+ years of industry experience, MS & 5 + years of industry experience, or PhD & 3+ years of industry experience• Must possess creative problem solving skills and technical spark• Must be effective at driving solutions across multiple groups and be passionate about work• Expertise in high speed logic design (clocking, timing, synchronization), and synthesizable RTL design• Solid understanding of circuit design and I/O system architecture is required• Ability to facilitate and make tradeoffs in power, area and performance of semiconductor I/O interfaces• Post silicon/lab experience, high speed I/O experience and memory system design are preferred
Knowledge of the following is required:
• High speed IOs / signal integrity / system timing analysis• Digital ASIC design (verilog)• Familiar with some of the following high speed chip interfaces: PCI Express, SATA, FibreChannel, HyperTransport, or high performance processor FSB• Circuit design fundamentals• Memory systems a plus, particularly DDR2 or GDDR2/3, QDR SRAM interfaces• Experience with systems from initial concept through lab prototypes and production• Basic understanding of clocking architectures and building blocks CDR’s and closed loop PLL’s,• Basic understanding of signal conditioning techniques such as equalization or crosstalk cancellation