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 Sr Staff Circuit Design Engineer

Details
Country: USA
Location: Mountain View CA
Total applied: 40
Location:US-CA-Mountain View

Base Pay:N/A
Employee Type:Full-Time Employee

Industry:Semiconductor

Manages Others:no
Sr Staff Circuit Design Engineer

About Actel

An established fabless supplier of nonvolatile single-chip field-programmable gate array (FPGA) technologies, Actel Corporation leverages its comprehensive portfolio of silicon, tools, IP and support to offer global designers low power, highly secure and firm error immune solutions while achieving the fastest time to market and lowest total system cost.


About the position:

Will participate in the design and development of Actel's next generation rad-tolerant/rad-hard high density Flash FPGA (backed by Government funding). Will involve in feasibility study, mixed-signal chip design, TapeOut, and silicon validation of >1M gate 90nm rtFlash FPGA..


Job duties includes: feasibility study (idea creation, architecture, ISP programming, testability, rad-hard scheme), patent filing, spec and documentation writing, circuit and logic design (digital, analog, RTL), simulations and verifications, test bench generation, layout supervision, TapeOut support, silicon evaluation and validation, cross-functional team interfacing and collaboration in all activities.


Informal design group and work environment.

Key values, beliefs, and attitudes are: Initiative (self-motivated, self-confident, self-driven, self-learning, always strive for excellence);
Commitments (responsible, responsive, commit to winning);
Solid functional and technical skills.Work quality ("Do it right the first time", attention to details, thorough in thinking and working, follow through with good documentations);Clear communication, cooperative team playing.


US Citizenship required. REQUIREMENTS
Experience and qualifications: MSMinimun of 5 years of applicable experienceCreative, like to play with ideas;Has good analytical and problem solving skill;Knows IC chip design, development flow, process, and methodology well;Knows CMOS logic design, circuit design, circuit analyses, and chip/cell layout floor planning well;Has good knowledge and understanding in solid state device physics, CMOS and Bipolar device operation and characteristics, as well as on topics such as Power Grid analysis, PowerUp/Down, SSO, Cross-talk, Metastability, ESD, Latchup, packaging, etc;Knowledge and experience in Analog circuit design and/or RTL design preferred;Knowledge in Radiation-Tolerance/Hardening a plus;Proficient with lab equipment operation and CAE/CAD tools (schematic capture, circuit simulations, design validation and verifications, etc);

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