ASIC Physical Designer

CTG is seeking an ASIC Physical Designer, who is interested in joining a team at our client site in Fishkill, NY.


The necessary skills are listed below:

Tools:

ChipBench

ChipEdit

PDS (Placement Driven Synthesis)



Skills:

ASIC Physical Design in cmos9sf (90nm). Experience with cmos8sf (130nm) will be acceptable. ASIC Physical Design includes: Floor planning, Circuit Placement, Wiring, Timing Closure, Clock insertion.

The person in this position will assist a physical design team, which is responsible for the creation of high speed SerDes for the ASIC Library. As part of this work, the team needs to create full ASIC chips that are used to certify the SerDes and the integration methodology. The requirement for this position is a person who is recently familiar with the IBM ASIC physical design tools and methodology. The chip design is taken from conception, C4 assignments, I/O placement, floor planning, clock insertion, circuit placement and wiring, through to timing closure and full checking.
REQUIREMENTS
Interested candidates should forward their resume to:


Melanie Delaney

Senior Technical Recruiter

CTG

[Click here for email]

www.ctg.com