ASIC Design Verification Engineer

SGI is seeking a Senior Design Verification Engineer to join our experienced team in Chippewa Falls, WI.
In this role: Candidate will do pre-silicon functional validation of ASIC?s designed for SGI?s next generation scalable shared-memory computer system. The focus of this role will be full-chip and system level verification and would include the following tasks: Designing test environments, Developing test stimulus codes, Analysis/debug of logic designs, and Developing and implementing test plans. REQUIREMENTS
{EDUCATION} BS/MS in Computer Engineering, Electrical Engineering, Computer Science or equivalent experience. At least 5 years of experience in Design Verification of large ASIC s. Candidate must have excellent, C, C++ and Perl skills. Must have a good understanding of advanced computer architectures that include front side bus protocols, memory subsystems, cache coherency concepts and distributed shared memory. This role requires an analytical approach for constructing tests and debug. Real-world post-silicon bring-up experience is desirable. Experience with Formal Verification methods is a plus.